1. Field of the Invention
The present invention relates to a design method for a semiconductor integrated circuit device.
2. Description of the Related Art
Recently various functions are integrated in semiconductor integrated circuit devices, and the performance to be demanded is becoming dramatically higher. Generally automatic designing using EDA tools are inferior to full customization designing, where most designing is manually performed, in terms of performance of designed semiconductor integrated circuits. On the other hand, an automatic design flow is demanded for decreasing the design period (TAT), process portability and ease of testing. In these aspects, increasing the performance of semiconductor integrated circuits designed by an automatic design flow using EDA tools is a critical issue.
As a method for increasing the speed for automatic design flow using EDA tools, the optimization of drive capability and the optimization of the number of outputs are used, which are known in the following (1), (2) and (3):
(1) Michel R. C. M. Berkelaar, Jochen A. G Jess, “Gate Sizing in MOS Digital Circuits with Linear Programming”, 1990, EDAC′90, [searched on Sep. 8, 2003],
(2) Oliver Coudert, et al, “New Algorithms for Gate Sizing: A Comparative Study”, 1996, DAC′96, [searched on Sep. 8, 2003],
(3) “A Fast Fan-out Optimization Algorithm for Near-Continuous Buffer Libraries”, 1998, DAC′98, [searched on Sep. 8, 2003],
These technologies are the processings to be executed as optimization processings when the logic synthesis in conventional EDA tools is performed. The optimization of drive capability is a method for minimizing the signal arrival time on a path in a device by adjusting the drive force of the elements constituting a semiconductor integrated circuit device. The optimization of number of outputs, on the other hand, is a method for decreasing the number of the components to be connected to an output of a component using a repeater or buffer when many components are connected, so as to minimize the signal arrival time of a path.
FIG. 17 is a diagram depicting the conventional design method for a semiconductor integrated circuit device. This design method comprises a logic synthesis processing in step S171, a layout optimization processing in step S172, a layout processing in step S173, and a delay calculation processing in step S174. This method includes the necessary processing from the point when RTL, a circuit diagram of the semiconductor integrated circuit device, is created, to when the layout is created. In detail, when the delay calculation processing S174 is executed and it is discerned that the path in the device does not satisfy the desired signal arrival time, the processing returns to step S171 or step S172 or step S173, and redesigning is performed so as to satisfy the desired arrival time.
FIG. 18 is a circuit diagram depicting the semiconductor integrated circuit device designed by the conventional design method, wherein a plurality of components constituting the inside of the semiconductor integrated circuit device and the connection relationship thereof are shown. Components 1, 2 and 3 are elements for holding the logic values inside the circuit. Components 4-10 are components of which the output signals are determined by input signals, such as an AND gate and OR gate. Reference number 11 denotes a combined circuit, which is comprised of components similar to the components 4-10.
When a semiconductor integrated circuit device is designed using a combination of such components, the signal arrival time, when a signal passes through each component, is calculated based on the signal transfer time to be input to each component and other components to be connected to the output. The longest signal arrival time, out of the signal arrival times from the components 1 and 2 to the component 3, determines the performance of the device. In this case, when the path passing through the components 1, 7, 9, 11 and 3 takes the longest signal arrival time, this path determines the performance of the semiconductor integrated circuit device.
This prior art, however, has limitations in increasing performance and in increasing the speed of the semiconductor integrated circuit device.